Efficient usage of Back End of Line (BEOL) routing resources continues to be an important factor in achieving reduction in both die scale and costs of chip design. Emphasis is typically placed on narrowing the wire pitch and overall footprint of chip components, particularly in heavy traffic areas such as the Metal-2 (M2) and Metal-3 (M3) layers. Despite these efforts, space constraints in heavy traffic area continues to be an issue in need of improvement especially as demand rises for more complex chips of increasingly smaller sizes.